1. Field of the Invention
The present relates generally to the recovery of a source node service clock at a destination node in a broadband asynchronous transfer mode (ATM) telecommunications network where reference timing signals derived from a master clock are available to both the source and destination nodes. More particularly, the present invention relates to apparatus and methods utilizing closed loop clock recovery for source frequencies which have been encoded according to a synchronous residual time stamp (SRTS) encoding technique.
2. State of the Art
Asynchronous Transfer Mode (ATM) is a packet oriented technology which permits continuous bit rate signals carrying one or more of voice, video, and data, to be conveyed across a netowrk within packets. ATM is suitable for the transport of bursty traffic such as data, as well as accommodating constant or continuous bit rate signals. In delivering continuous bit rate traffic (e.g., T1, DS3 signals) in a broadband network, the clock controlling the destination node buffer must operate at a frequency precisely matched to that of the service signal input at the source node in order to avoid buffer overflow or underflow and resulting loss of data. However, the clock frequency at the destination node cannot easily be traced directly back to that of the source, because the ATM network inherently introduces cell jitter; i.e., random delay and aperiodic arrival of cells at a destination node, which corrupts the value of the cell arrival times and makes their use more difficult as a means for directly recovering the original service signal input frequency.
Numerous schemes have been proposed to provide a mechanism for recovering service timing in the presence of cell jitter. Descriptions of many of these schemes are provided in Fleischer et al. U.S. Pat. No. 5,260,978, which is hereby incorporated by reference in its entirety herein. Perhaps the most elegant and widely accepted of the clock recovery schemes is known as synchronous residual time stamp (SRTS) encoding which is the subject matter of the Fleischer et al. patent.
In the preferred embodiment of SRTS encoding according to Fleischer et al., a free-running four bit counter is used at the source node to count cycles of a common network clock. At the end of every residual time stamp (RTS) time period formed by 3008 service clock cycles (i.e., eight cells of forty-seven bytes of data each), the current four bit count of the P-bit counter is transmitted in the ATM adaptation layer (AAL1) by using one bit in every other of byte of the AAL1 for eight cells. It should be noted that the AAL1 is the overhead byte which accompanies the forty-seven bytes of data to constitute the forty-eight-byte payload of an ATM cell. The ATM cell also includes five additional bytes of header. The four-bit SRTS provides sufficient information for unambiguously representing the number of network clock cycles within a predetermined range.
The clock recovery at the destination node according to Fleischer et al. involves determining from the received RTSs the number of network clock cycles in each RTS period, and generating a pulse signal from the network clock in which the period of the pulse equals the determined number of network clock cycles in the corresponding RTS period. The pulse signal frequency is then multiplied by 3008 in order to recover the source node service clock.
While the clock recovery mechanism of Fleischer et al. might be suitable for recovering the source node service clock, it is neither the only recovery mechanism possible, nor necessarily the most optimal mechanism for recovering the source node service clock.